![Figure 3 from P-minus substrate guard ring modeling for the purpose of noise isolation in CMOS substrates | Semantic Scholar Figure 3 from P-minus substrate guard ring modeling for the purpose of noise isolation in CMOS substrates | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/838b43d15893cf71505b2d60e2471fd96c7e2946/3-Figure3-1.png)
Figure 3 from P-minus substrate guard ring modeling for the purpose of noise isolation in CMOS substrates | Semantic Scholar
![The impact of electromagnetic coupling of guard ring metal lines on the performance of On-chip spiral inductor in silicon CMOS | Semantic Scholar The impact of electromagnetic coupling of guard ring metal lines on the performance of On-chip spiral inductor in silicon CMOS | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/fa1f820967df916acc187aaff1a99d423f09aff4/3-Figure4-1.png)
The impact of electromagnetic coupling of guard ring metal lines on the performance of On-chip spiral inductor in silicon CMOS | Semantic Scholar
![Guard rings: Structures, design methodology, integration, experimental results, and analysis for RF CMOS and RF mixed signal BiCMOS silicon germanium technology - ScienceDirect Guard rings: Structures, design methodology, integration, experimental results, and analysis for RF CMOS and RF mixed signal BiCMOS silicon germanium technology - ScienceDirect](https://ars.els-cdn.com/content/image/1-s2.0-S0304388606000519-gr6.jpg)
Guard rings: Structures, design methodology, integration, experimental results, and analysis for RF CMOS and RF mixed signal BiCMOS silicon germanium technology - ScienceDirect
![US8110853B2 - Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication - Google Patents US8110853B2 - Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication - Google Patents](https://patentimages.storage.googleapis.com/03/02/04/3f1de4ce57c824/US08110853-20120207-D00000.png)
US8110853B2 - Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication - Google Patents
![Single-event multiple transients in guard-ring hardened inverter chains of different layout designs - ScienceDirect Single-event multiple transients in guard-ring hardened inverter chains of different layout designs - ScienceDirect](https://ars.els-cdn.com/content/image/1-s2.0-S0026271418304104-gr8.jpg)
Single-event multiple transients in guard-ring hardened inverter chains of different layout designs - ScienceDirect
![GUARD RING STRUCTURES FOR HIGH VOLTAGE CMOS/LOW VOLTAGE CMOS TECHNOLOGY USING LDMOS (LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR) DEVICE FABRICATION - diagram, schematic, and image 03 GUARD RING STRUCTURES FOR HIGH VOLTAGE CMOS/LOW VOLTAGE CMOS TECHNOLOGY USING LDMOS (LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR) DEVICE FABRICATION - diagram, schematic, and image 03](https://www.patentsencyclopedia.com/img/20090236662_03.png)
GUARD RING STRUCTURES FOR HIGH VOLTAGE CMOS/LOW VOLTAGE CMOS TECHNOLOGY USING LDMOS (LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR) DEVICE FABRICATION - diagram, schematic, and image 03
![Cross sections of the pixels (a–b) fabricated using 0.5- μ m technology... | Download Scientific Diagram Cross sections of the pixels (a–b) fabricated using 0.5- μ m technology... | Download Scientific Diagram](https://www.researchgate.net/profile/Igor-Brouk/publication/3075281/figure/fig1/AS:279975430246414@1443762752864/Cross-sections-of-the-pixels-a-b-fabricated-using-05-m-m-technology-process-within.png)
Cross sections of the pixels (a–b) fabricated using 0.5- μ m technology... | Download Scientific Diagram
![Figure 1 from Guard Ring Interactions and their Effect on CMOS Latchup Resilience | Semantic Scholar Figure 1 from Guard Ring Interactions and their Effect on CMOS Latchup Resilience | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/a5808033f6ff229ad96dc620f0cd5d618d6d3fce/3-Figure1-1.png)
Figure 1 from Guard Ring Interactions and their Effect on CMOS Latchup Resilience | Semantic Scholar
Parasitic inductances of the ground connection and of the guard ring... | Download Scientific Diagram
![Guard rings: Structures, design methodology, integration, experimental results, and analysis for RF CMOS and RF mixed signal BiCMOS silicon germanium technology - ScienceDirect Guard rings: Structures, design methodology, integration, experimental results, and analysis for RF CMOS and RF mixed signal BiCMOS silicon germanium technology - ScienceDirect](https://ars.els-cdn.com/content/image/1-s2.0-S0304388606000519-gr4.jpg)
Guard rings: Structures, design methodology, integration, experimental results, and analysis for RF CMOS and RF mixed signal BiCMOS silicon germanium technology - ScienceDirect
![Guard rings: Structures, design methodology, integration, experimental results, and analysis for RF CMOS and RF mixed signal BiCMOS silicon germanium technology - ScienceDirect Guard rings: Structures, design methodology, integration, experimental results, and analysis for RF CMOS and RF mixed signal BiCMOS silicon germanium technology - ScienceDirect](https://ars.els-cdn.com/content/image/1-s2.0-S0304388606000519-gr3.jpg)
Guard rings: Structures, design methodology, integration, experimental results, and analysis for RF CMOS and RF mixed signal BiCMOS silicon germanium technology - ScienceDirect
![Guard rings: Structures, design methodology, integration, experimental results, and analysis for RF CMOS and RF mixed signal BiCMOS silicon germanium technology - ScienceDirect Guard rings: Structures, design methodology, integration, experimental results, and analysis for RF CMOS and RF mixed signal BiCMOS silicon germanium technology - ScienceDirect](https://ars.els-cdn.com/content/image/1-s2.0-S0304388606000519-gr2.jpg)